To achieve low-power operation, the team actually focused on nonoperation—the idle time that makes up more than 99 percent of the device’s lifetime. In sleep mode, power gates, which are transistors that act as simple switches, block electrical current from running. In standard designs, those gates are wide to provide lower resistance when the device is turned on. But the low resistance means that even with the gate closed, a fair amount of current leaks through, wasting power. To reduce the leakage, the team went back to an older design generation. Today’s chips have 45-nanometer features. The Michigan team went back four generations to the 180-nm node, creating longer, more-resistive gates. At the same time, they made them narrower, which also raises resistance. The downside is that when the device is actually running, it requires an extra 100 millivolts to overcome the gate’s added resistance. But because the chip is active for only a small fraction of the time—a few hundred milliseconds every 10 minutes—overall power use is still reduced.
Source: IEEE Spectrum.
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